1. Field of the Invention
This invention relates to an operational amplifier for buffering and/or amplifying a signal and, more particularly, to an operational amplifier having an offset compensation function. This invention is also directed to a digital-to-analog (D/A) converter for converting digital data to analog signals employing the operational amplifier.
2. Description of the Background Art
Generally, various types of operational amplifiers have been used to buffer signals, to amplify the magnitude of the signals, and to add the signals to each other. Operational amplifiers are used in various electrical circuits including a D/A converter and a liquid crystal panel driving circuit.
In a liquid crystal display (LCD) device, a conventional operational amplifier includes thin film transistors (TFTs), and is connected to an output buffer and a D/A converter of the liquid crystal panel driving circuit. The TFTs are fabricated by polysilicon, which has inferior characteristic compared to silicon. The TFTs fabricated using a polysilicon material, act as a dominance source for increasing an offset voltage in the operational amplifier.
An offset compensation circuit can be provided in the operational amplifier to eliminate the increased offset voltage. A conventional offset compensation circuit provided in the operational amplifier reduces the offset voltage by controlling the current of the operational amplifier. The offset compensation circuit eliminates any offset voltage which is less than a set limit, but does not eliminate an offset voltage which is greater than the set limit. Further, it is difficult to eliminate an offset voltage in the operational amplifier which is formed with a polysilicon material. These problems of the conventional art will be apparent from the following description with reference to FIGS. 1 and 2.
Referring to FIG. 1, a conventional offset compensation circuit is provided with first to third TFTs T1-T3 for responding to a reset signal RET output from a control line 11, and a first capacitor C1 connected between a non-inverting terminal (+) of an operational amplifier A1 and a first node N1. The first to third TFTs T1-T3 are turned on when the reset signal RET remains at a high logic level, thereby allowing an output signal of the operational amplifier A1 to be charged into the first capacitor C1. Since the first TFT T1 is turned on, the first TFT T1 connects the output terminal of the operational amplifier A1 to an inverting terminal (-) of the operational amplifier A1, and provides the output signal of the operational amplifier A1 to the inverting terminal (-) of the amplifier A1 as a feedback output signal. The second TFT T2 charges the feedback output signal, via the first node N1, into the first capacitor C1. Since the third TFT T3 is turned on, the third TFT T3 connects the non-inverting terminal (+) of the operational amplifier A1 to the ground GND. As a result, the first capacitor C1 is coupled between the inverting terminal (-) of the operational amplifier A1 and the ground GND to thereby charge the feedback output signal into the first capacitor C1.
The conventional offset compensation circuit of FIG. 1 further includes an inverter INV1 for inverting the reset signal RET, and a fourth TFT T4 for responding to the inverted reset signal /RET. The fourth TFT T4 connects the first node N1 to the ground GND when the reset signal RET remains at a low logic level, thereby allowing a voltage charged in the first capacitor C1 to be discharged to the non-inverting terminal (+) of the operational amplifier A1.
As described above, the conventional offset compensation circuit for operational amplifiers samples the output signal of the operational amplifier A1 and applies the sampled output signal to an input terminal of the operational amplifier A1 in an inverted shape, thereby reducing the offset voltage. In other words, the conventional offset compensation circuit provides a negative feedback of the output signal of the operational amplifier to the non-inverting terminal of the operational amplifier to reduce the offset voltage.
FIG. 2 shows a circuitry of the operational amplifier A1 of FIG. 1. As shown in FIG. 2, the operational amplifier A1, responding to a negative feedback signal, includes a high voltage line 12, fourth and sixth TFTs T5 and T6 connected in a current mirror type configuration between second and third nodes N2 and N3, a seventh TFT T7 connected between the second node N2 and a fourth node N4, an eighth TFT T8 connected between the third and fourth nodes N3 and N4, and a ninth TFT T9 connected between the fourth node N4 and a low voltage line 13. The high voltage line 12 is connected to a high voltage source VDD, and the low voltage line 13 is connected to a low voltage source VSS. The seventh TFT T7 controls an amount of current flowing from the second node N2 into the fourth node N4 based on an input signal at the inverting terminal (-), thereby producing an amplified signal at the third node N3. The eighth TFT T8 controls an amount of current flowing from the third node N3 into the fourth node N4 based on the feedback output signal from the non-inverting terminal (+), thereby reducing an offset voltage included in the output signal produced at the third node N3. The ninth TFT T9 constantly maintains the amount of current flowing from the fourth node N4 voltage to the low voltage source VSS via the low voltage line 13 by controlling a bias voltage signal produced from a bias line 14.
The operational amplifier A1 further includes a tenth TFT T10 connected between the high voltage line 12 and a fifth node N5, a second capacitor C2 between the third node N3 and the fifth node N5, and an eleventh TFT T11 connected between the fifth node N5 and the low voltage line 13. The tenth TFT T10 controls an amount of current flowing from the high voltage line 12 into the fifth node N5 based on a voltage on the third node N3 to amplify the voltage on the third node N3. The eleventh TFT T11 keeps a channel width corresponding to the bias voltage from the bias line 14 to maintain a constant resistance value.
The conventional operational amplifier as described above generates an offset voltage due to differences between the seventh and eighth TFTs T7 and T8, between the eighth and ninth TFTs T8 and T9, and between the ninth and eleventh TFTs T9 and T11. This offset voltage increases when the ninth TFT T9 has different characteristics from the TFTs T7, T8 and T11, and the increased offset voltage is not reduced below a certain limit although a mirror current is controlled by the feedback output signal. This is caused by the fact that an amount of current passing through the ninth TFT T9 does not change even though the mirror current is controlled. The offset voltage further increases when the TFTs are formed with a polysilicon material rather than silicon. Generally, an operational amplifier formed with silicon TFTs generates an offset voltage of about 10 mV while an operational amplifier formed with polysilicon TFTs generates an offset voltage of several volts. For instance, when a threshold voltage (Vth) difference between the polysilicon TFTs is 2V, the conventional operational amplifier generates a large offset voltage of about 2V. When the difference in the carrier drift degree (.mu.) of each polysilicon TFT is about 40 cm.sup.2 /Vsec, the conventional operational amplifier generates a large offset voltage of approximately 1 V.